Libre/OpenCores FuseSoc backend

Chip (FPGA/ASIC) development is normally done in a very hierarchical manner where gateware is used to build up subsystems which are combined to a full chip design. On paper, this leans

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ProjectID

FuseSoc-Cores

Acronym

FuseSoc-Cores

Additional Info

Not available yet

Enduser Relevance

Open collaboration (like for example on open source software) is based on the premise that together, we know more than we do alone. For open source software development, there is a

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https://nlnet.nl/contact/

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Country:  Netherlands United Kingdom

Keyword: ASICFPGARepository

Status: -

Category: Trustworthy hardware and manufacturing

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